This invention relates generally to the field of integrated circuit devices, and more specifically to sampling of multiple nodes within an integrated circuit.
Sampling on the fly (SOF) is a technique used to sample a large number of nodes with scan latches and then scan out the data before the scan latches are updated. This technique may be applied, for example, to sample multiple nodes of a processor architecture during the test and debug phase of the processor development cycle. In such an example, SOF may be used to non-invasively evaluate the performance of the integrated circuit by taking snapshots of bus and module values at various points of operation. One important aspect of sample on the fly is the timing related to the scan operation. If N nodes are to be scanned, then ideally the N nodes would be scanned in the same clock cycle. Moreover, if an integrated circuit supports synchronous and asynchronous operation, then sampling N nodes during a minimum number of clock cycles is a difficult task.
According to a system of the present invention, a SOF circuit for sample on the fly synchronization of multiple nodes of an integrated circuit with minimal clock cycle delay is disclosed. The integrated circuit may contain several circuits where each circuit has multiple bus clocks and multiple bus clock domains. The SOF circuit, which may operate synchronous or a synchronously, is coupled to the circuits and generates an UPDATE signal that can latch the multiple nodes of the integrated circuit. The value of the UPDATE signal is controlled by a setreset flip-flop circuit. The set-reset flip-flop circuit sets or resets the value of the UPDATE signal so that correct latching of the multiple nodes occurs. The synchronous and asynchronous nature of the multiple bus clocks is addressed by a metastable rejection circuit. The metastable rejection circuit ensures that all nodes can be latched when the UPDATE signal is received by the SOF circuit. In accordance with a method of the present invention, the SOF circuit receives a read signal that enables the latching of the multiple nodes. The flip-flop circuit generates a sample signal after the flip-flop circuit receives a set signal from the multiple bus clocks. The SOF circuit receives the sample signal from the flip-flop circuit, and the sample signal is able to latch onto a clock of the multiple bus domain clocks. The read signal is combined with the latched sample signal to generate the UPDATE signal. In an asynchronous system, the set signal may come in a metastable problem time period. In that case, an insufficient pulse width UPDATE signal goes through the metastable rejection circuit. The metastable rejection circuit ensures that the UPDATE signal has a sufficient pulse width to latch the multiple nodes.